Merge pull request #1 from kivikakk/c2n

Use Niar.

.github/workflows/cxxrtl-build.yml

@@ -1,4 +1,4 @@
-name: cxxrtl build
+name: CXXRTL build
 
 on:
   push:
@@ -11,22 +11,20 @@ permissions:
 
 jobs:
   cxxrtl-build:
-    runs-on: ubuntu-24.04
+    runs-on: ubuntu-latest
     steps:
     - name: Checkout repo
       uses: actions/checkout@v4
 
-    - name: Set up Chryse
-      uses: chryse-hdl/setup-chryse@v2
+    - name: Install pip dependencies
+      run: pip install --editable .
+
+    - uses: kivikakk/niar/setup-action@main
       with:
-        source-ref: main
-        athena-source-ref: main
-        install-oss-cad-suite: true
-        github-token: ${{ secrets.GITHUB_TOKEN }}
-        install-zig: 0.13.0
+        install-zig: '0.13.0'
 
     - name: Install SDL
       run: sudo apt-get install -y libsdl2-dev
 
     - name: Elaborate and compile cxxrtl
-      run: sbt 'run cxxrtl -c'
+      run: python -m ili9341spi cxxrtl -c

.github/workflows/synthesis.yml

@@ -11,26 +11,26 @@ permissions:
 
 jobs:
   synthesis:
-    runs-on: ubuntu-24.04
+    runs-on: ubuntu-latest
 
     strategy:
       fail-fast: false
       matrix:
         board:
         - icebreaker
-        - ulx3s-45f
+        - ulx3s
 
     steps:
     - name: Checkout repo
       uses: actions/checkout@v4
 
-    - name: Set up Chryse
-      uses: chryse-hdl/setup-chryse@v2
+    - name: Install pip dependencies
+      run: pip install --editable .
+
+    - uses: kivikakk/niar/setup-action@main
       with:
-        source-ref: main
-        athena-source-ref: main
         install-oss-cad-suite: true
         github-token: ${{ secrets.GITHUB_TOKEN }}
 
     - name: Elaborate and synthesise
-      run: sbt 'run build -b ${{ matrix.board }}'
+      run: python -m ili9341spi build -b ${{ matrix.board }}

.github/workflows/unit-tests.yml

@@ -11,16 +11,15 @@ permissions:
 
 jobs:
   unit-tests:
-    runs-on: ubuntu-24.04
+    runs-on: ubuntu-latest
     steps:
     - name: Checkout repo
       uses: actions/checkout@v4
 
-    - name: Set up Chryse
-      uses: chryse-hdl/setup-chryse@v2
-      with:
-        source-ref: main
-        athena-source-ref: main
+    - name: Install pip dependencies
+      run: pip install --editable .
+
+    - uses: kivikakk/niar/setup-action@main
 
     - name: Run tests
-      run: sbt test
+      run: pytest tests

.gitignore

@@ -1,16 +1,6 @@
-build/
+__pycache__
+/build
 *.vcd
+
 .zig-cache/
 zig-out/
-rom.bin
-
-target/
-test_run_dir/
-
-.cache/
-.metals/
-.bloop/
-.bsp/
-metals.sbt
-
-.DS_Store

.vscode/settings.json

@@ -1,6 +1,13 @@
 {
-    "files.watcherExclude": {
-        "**/target": true
+    "[python]": {
+        "editor.codeActionsOnSave": {
+            "source.organizeImports": "explicit"
+        }
     },
-    "editor.formatOnSave": true,
+    "python.analysis.autoImportCompletions": true,
+    "python.analysis.diagnosticSeverityOverrides": {
+        "reportGeneralTypeIssues": "none",
+        "reportAttributeAccessIssue": "information",
+        "reportArgumentType": "information"
+    }
 }

cxxrtl/src/SimThread.zig

@@ -3,7 +3,6 @@ const std = @import("std");
 const Cxxrtl = @import("./Cxxrtl.zig");
 const SimController = @import("./SimController.zig");
 const SpiConnector = @import("./SpiConnector.zig");
-const UartConnector = @import("./UartConnector.zig");
 
 const SimThread = @This();
 
@@ -18,11 +17,10 @@ alloc: std.mem.Allocator,
 cxxrtl: Cxxrtl,
 vcd: ?Cxxrtl.Vcd,
 
-clock: Cxxrtl.Object(bool),
-reset: Cxxrtl.Object(bool),
+clk: Cxxrtl.Object(bool),
+rst: Cxxrtl.Object(bool),
 
 spi_connector: SpiConnector,
-uart_connector: UartConnector,
 
 img_data: ImgData = [_]Color{.{ .r = 0, .g = 0, .b = 0 }} ** (HEIGHT * WIDTH),
 img_data_new: bool = true,
@@ -33,21 +31,19 @@ pub fn init(alloc: std.mem.Allocator, sim_controller: *SimController) SimThread
     var vcd: ?Cxxrtl.Vcd = null;
     if (sim_controller.vcd_out != null) vcd = Cxxrtl.Vcd.init(cxxrtl);
 
-    const clock = cxxrtl.get(bool, "clock");
-    const reset = cxxrtl.get(bool, "reset");
+    const clk = cxxrtl.get(bool, "clk");
+    const rst = cxxrtl.get(bool, "rst");
 
     const spi_connector = SpiConnector.init(cxxrtl);
-    const uart_connector = UartConnector.init(cxxrtl, @embedFile("rom.bin"));
 
     return .{
         .sim_controller = sim_controller,
         .alloc = alloc,
         .cxxrtl = cxxrtl,
         .vcd = vcd,
-        .clock = clock,
-        .reset = reset,
+        .clk = clk,
+        .rst = rst,
         .spi_connector = spi_connector,
-        .uart_connector = uart_connector,
     };
 }
 
@@ -58,9 +54,9 @@ pub fn deinit(self: *SimThread) void {
 
 pub fn run(self: *SimThread) !void {
     self.sim_controller.lock();
-    self.reset.next(true);
+    self.rst.next(true);
     self.cycle();
-    self.reset.next(false);
+    self.rst.next(false);
     self.sim_controller.unlock();
 
     // XXX: We handle barely any of MADCTL, so this is incredibly specific to
@@ -105,7 +101,6 @@ pub fn run(self: *SimThread) !void {
                     state = .MemoryWriteA;
                     col = sc;
                     pag = sp;
-                    self.uart_connector.go();
                 } else {
                     state = .Idle;
                 }
@@ -172,18 +167,17 @@ pub fn run(self: *SimThread) !void {
                 }
             },
         }
-        self.uart_connector.tick();
     }
 
     try self.writeVcd();
 }
 
 fn cycle(self: *SimThread) void {
-    self.clock.next(false);
+    self.clk.next(false);
     self.cxxrtl.step();
     if (self.vcd) |*vcd| vcd.sample();
 
-    self.clock.next(true);
+    self.clk.next(true);
     self.cxxrtl.step();
     if (self.vcd) |*vcd| vcd.sample();
 

cxxrtl/src/SpiConnector.zig

@@ -5,7 +5,6 @@ const Cxxrtl = @import("./Cxxrtl.zig");
 const SpiConnector = @This();
 
 cipo: Cxxrtl.Object(bool),
-blk: Cxxrtl.Sample(bool),
 dc: Cxxrtl.Sample(bool),
 res: Cxxrtl.Sample(bool),
 copi: Cxxrtl.Sample(bool),
@@ -21,16 +20,14 @@ const Tick = union(enum) {
 };
 
 pub fn init(cxxrtl: Cxxrtl) SpiConnector {
-    const cipo = cxxrtl.get(bool, "spi_cipo");
-    const blk = Cxxrtl.Sample(bool).init(cxxrtl, "spi_blk", false);
-    const dc = Cxxrtl.Sample(bool).init(cxxrtl, "spi_dc", false);
-    const res = Cxxrtl.Sample(bool).init(cxxrtl, "spi_res", false);
-    const copi = Cxxrtl.Sample(bool).init(cxxrtl, "spi_copi", false);
-    const clk = Cxxrtl.Sample(bool).init(cxxrtl, "spi_clk", false);
+    const cipo = cxxrtl.get(bool, "lcd__cipo");
+    const dc = Cxxrtl.Sample(bool).init(cxxrtl, "lcd__dc", false);
+    const res = Cxxrtl.Sample(bool).init(cxxrtl, "lcd_res", false);
+    const copi = Cxxrtl.Sample(bool).init(cxxrtl, "lcd__copi", false);
+    const clk = Cxxrtl.Sample(bool).init(cxxrtl, "lcd__clk", false);
 
     return .{
         .cipo = cipo,
-        .blk = blk,
         .dc = dc,
         .res = res,
         .copi = copi,