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Pull requests: intel/rohd

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Pull requests list

Adding mechanisms to remove redundant parentheses.
#586 opened Mar 8, 2025 by gus-bonilla-86 Loading…
2
SystemVerilog block labels
#585 opened Mar 8, 2025 by lucasphillips Loading…
1
9
Adding mechanisms to avoid unnecessary swizzle conversions.
#584 opened Mar 8, 2025 by gus-bonilla-86 Loading…
1
2
Enhance LogicValue.toRadixString to enable fixed-width output
#583 opened Mar 7, 2025 by desmonddak Loading…
1
4
Avoid Module creation for Constant Gate scenarios
#481 opened Apr 5, 2024 by mjayasim9 Loading…
1
10
Vscode extension
#437 opened Nov 14, 2023 by quekyj Loading…
18
[WIP] Add local Markdown checks
#330 opened Mar 22, 2023 by chykon • Draft
Automatically check for new Dart lints
#284 opened Feb 24, 2023 by chykon • Draft
2
Fix bug related to clock divider simulation, fix #191
#192 opened Nov 1, 2022 by mkorbel1 • Draft
1
3
ProTip! What’s not been updated in a month: updated:<2025-02-12.