Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

GateMate Constraint File Pin Declaration Format #10

Closed
tarik-hamedovic opened this issue Jun 8, 2024 · 7 comments
Closed

GateMate Constraint File Pin Declaration Format #10

tarik-hamedovic opened this issue Jun 8, 2024 · 7 comments
Assignees
Labels
enhancement New feature or request help wanted Extra attention is needed

Comments

@tarik-hamedovic
Copy link
Collaborator

The current constraint format for GateMate chips requires the declaration of pin directions both in the constraint file and the HDL file such as Pin_in, Pin_out, Pin_inout. This approach is unconventional and differs from other vendors, creating challenges in implementing Amaranth HLS for GateMate chips. The primary issue is the inability to create a general constraint file due to the necessity of specifying pin directions in the constraint file.

Proposed Solution

To resolve this issue, it is suggested to use a general pin constraint format that only requires the pin identifier, without the need to specify its direction in the constraint file. This would align with common practices and facilitate easier implementation and integration with Amaranth HLS.

By adopting this improvement, the workflow for developing with GateMate chips would become more streamlined and user-friendly, aligning better with industry standards.

@chili-chips-ba
Copy link
Owner

chili-chips-ba commented Jun 8, 2024

@pu-cc , @whitequark for awareness. Also see: amaranth-lang/amaranth#1372 (comment)

@chili-chips-ba
Copy link
Owner

chili-chips-ba commented Jun 9, 2024

... given Yosys SV problems, one option to consider is to move all new design creation to Amaranth. While that's a no brainer for other vendors, these CologneChip constraints peculiarities stand in the way of adopting such development flow for GateMate.

@whitequark
Copy link

I am not a part of your team nor am I responsible for addressing this issue.

@whitequark whitequark removed their assignment Jun 17, 2024
@chili-chips-ba chili-chips-ba added the bug Something isn't working label Jul 10, 2024
@chili-chips-ba
Copy link
Owner

@DadoCCAG , given that it seems very difficult for Amaranth to adapt to this GateMate uniqueness of the constraints' format, what's your assessment from CologneChip side on the chance for providing an option that would align it with other FPGA vendors?

The objective is to enable GateMate in Amaranth flow, making the first critical step towards HLS, and opening a whole new set of possible applications.

@chili-chips-ba chili-chips-ba added enhancement New feature or request help wanted Extra attention is needed and removed bug Something isn't working labels Jul 13, 2024
@pu-cc
Copy link
Collaborator

pu-cc commented Jul 17, 2024

With the upcoming P&R update, CCF will now offer the option of specifying the keyword “NET” instead of the pin direction. P&R then retrieves the direction information from the buffer primitives in the netlist. This is compatible with the UCF file format.

As soon as the update is online, I will report it here to close #10.

@chili-chips-ba
Copy link
Owner

... that's a wise approach, one that both retains compatibility with CC legacy, and gains compatibility with everything else 💯

@pu-cc
Copy link
Collaborator

pu-cc commented Jul 19, 2024

We updated the P&R binary yesterday. CCF now supports the “NET” keyword as described here. You can download the latest build it here:

https://colognechip.com/downloads/cc-toolchain-linux.tar.gz
https://colognechip.com/downloads/cc-toolchain-win.zip

Thanks for your help.

@pu-cc pu-cc closed this as completed Jul 19, 2024
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
enhancement New feature or request help wanted Extra attention is needed
Projects
None yet
Development

No branches or pull requests

5 participants