Winch: i8x16.shuffle for x64 with AVX #9959
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jeffcharles
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I can take this review as well. |
saulecabrera
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jeffcharles
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winch/codegen/src/isa/x64/masm.rs
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| if self.flags.has_avx() { | ||
| // Use `vpshufb` with `lanes` to set the lanes in `lhs` and `rhs` | ||
| // separately to either the selected index or 0. | ||
| // Then use `vpor` to combine `lhs` and `rhs` into `dst`. | ||
| // Setting the most significant bit in the mask's lane to 1 will | ||
| // result in corresponding lane in the destination register being | ||
| // set to 0. 0x80 sets the most significant bit to 1. | ||
| let mut mask_lhs: [u8; 16] = [0x80; 16]; | ||
| let mut mask_rhs: [u8; 16] = [0x80; 16]; | ||
| for i in 0..lanes.len() { | ||
| if lanes[i] < 16 { | ||
| mask_lhs[i] = lanes[i]; | ||
| } else { | ||
| mask_rhs[i] = lanes[i] - 16; | ||
| } | ||
| } | ||
| let mask_lhs = self.asm.add_constant(&mask_lhs); | ||
| let mask_rhs = self.asm.add_constant(&mask_rhs); | ||
|
|
||
| self.asm.xmm_vpshufb_rrm(dst, lhs, &mask_lhs); | ||
| let scratch = writable!(regs::scratch_xmm()); | ||
| self.asm.xmm_vpshufb_rrm(scratch, rhs, &mask_rhs); | ||
| self.asm.vpor(dst, dst.to_reg(), scratch.to_reg()); | ||
| } else { | ||
| bail!(CodeGenError::UnimplementedForNoAvx) | ||
| } | ||
| Ok(()) | ||
| } |
There was a problem hiding this comment.
One small suggestion perhaps to improve readability, given that the then branch is somewhat lengthy, could we invert the check so that we return early in case there's no avx support?
if !self.flags().has_avx() {
bail!(...);
}
// ....
Ok(())
saulecabrera
approved these changes
Jan 15, 2025
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Part of #8093. Implements
i8x16.shuffleon x64 with AVX extensions.