Winch: packed integer basic arithmetic for x64 #10147
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| /// Perform a vector add between `lsh` and `rhs`, placing the result in `dst`, where each lane | ||
| /// is interpreted to be `size` long. | ||
| fn v128_add( |
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naming-wise, I'm completely sure what to call those. Maybe vector_add is more appropriate?
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I think the naming is fine here, as far as I can tell, we don't have any other vector naming convention.
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I can take this review. |
saulecabrera
requested review from
saulecabrera
and removed request for
a team and
fitzgen
winch/codegen/src/isa/x64/masm.rs
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| let mul_avx512 = |this: &mut Self, op| { | ||
| this.ensure_has_avx512vl()?; | ||
| this.ensure_has_avx512dq()?; | ||
| this.asm.xmm_rm_rvex3(op, lhs, rhs, dst); | ||
| Ok(()) |
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I don't think we should make this a hard requirement, given that our baseline is AVX.
Given that Intel suggests that there's no penalty on mixing AVX with AVX512 instructions , we could emit AVX512 if they are available, however in case they aren't we still need to emit a fallback to avoid bumping our baseline for this operation. For reference: https://github.com/bytecodealliance/wasmtime/blob/main/cranelift/codegen/src/isa/x64/lower.isle#L1121
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my bad, I misunderstood your DM about what we expected to support. I have ported cranelift fallback implementation.
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hold on I just found a bug
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| /// Perform a vector add between `lsh` and `rhs`, placing the result in `dst`, where each lane | ||
| /// is interpreted to be `size` long. | ||
| fn v128_add( |
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I think the naming is fine here, as far as I can tell, we don't have any other vector naming convention.
MarinPostma
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implements the following instructions for winch x64:
i8x16.addi8x16.add_sat_ui8x16.add_sat_si16x8.addi16x8.add_sat_ui16x8.add_sat_si32x4.addi64x2.addi8x16.subi8x16.sub_sat_ui8x16.sub_sat_si16x8.subi16x8.sub_sat_ui16x8.sub_sat_si32x4.subi64x2.subi16x8.muli32x4.muli64x2.mul#8093