projects/dac_fmc_ebz: Changes for AD9163

[cristianmihaipopa]

PR Description

These following changes were made for AD9163:

• Added new transceiver parameters (QPLL1, for GTHE4) for a new supported lane rate: 4.16 GHz
• Modified S parameter for Mode 2 (previous was 2, should've been 1, according to the datasheet)
• Tested in hardware two modes, working as expected:
  • Mode 2 (12.5 GHz, 2 lanes): Works only with external clock source, the J61 jumper must be removed
  • Mode 8 (4.16 GHz, 8 lanes): Works with/without external clock source

Updated the copyright year for the rest of the files.
For each mode, a new devicetree was created, which can be seen in this PR: analogdevicesinc/linux#2711

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have compiled all hdl projects and libraries affected by this PR
• I have tested in hardware affected projects, at least on relevant boards
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Critical Warnings on compilation
• I have added new hdl testbenches or updated existing ones