output a regular clock too for LA.

Author: kivikakk

ili9341spi/rtl/__init__.py

@@ -1,4 +1,4 @@
-from amaranth import Module, Mux, Signal
+from amaranth import ClockSignal, Module, Mux, Signal
 from amaranth.build import Attrs, Pins, PinsN, Resource, Subsignal
 from amaranth.lib import wiring
 from amaranth.lib.cdc import FFSynchronizer
@@ -16,41 +16,25 @@
 __all__ = ["Top"]
 
 
-icebreaker_spi_lcd = Resource(
-    "spi_lcd",
-    0,
-    Subsignal(
-        "clk", Pins("3", dir="o", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")
-    ),
-    Subsignal(
-        "copi", Pins("4", dir="o", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")
-    ),
-    Subsignal(
-        "res", PinsN("7", dir="o", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")
-    ),
-    Subsignal(
-        "dc", PinsN("8", dir="o", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")
-    ),
-    Subsignal(
-        "blk", Pins("9", dir="o", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")
-    ),
-    Subsignal(
-        "cipo", Pins("10", dir="i", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")
-    ),
+icebreaker_spi_lcd = Resource("spi_lcd", 0,
+    Subsignal("clk",  Pins("3", dir="o", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")),
+    Subsignal("copi", Pins("4", dir="o", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")),
+    Subsignal("res",  PinsN("7", dir="o", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")),
+    Subsignal("dc",   PinsN("8", dir="o", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")),
+    Subsignal("blk",  Pins("9", dir="o", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")),
+    Subsignal("cipo", Pins("10", dir="i", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")),
 )
 
 
 class Top(wiring.Component):
     def __init__(self, platform):
         if isinstance(platform, cxxrtl):
-            super().__init__(
-                {
-                    "lcd": Out(Lcd.PinSignature),
-                    "lcd_res": Out(1),
-                    "uart_rx": In(1),
-                    "uart_tx": Out(1),
-                }
-            )
+            super().__init__({
+                "lcd": Out(Lcd.PinSignature),
+                "lcd_res": Out(1),
+                "uart_rx": In(1),
+                "uart_tx": Out(1),
+            })
         else:
             super().__init__({})
 
@@ -102,7 +86,8 @@ def elaborate(self, platform):
             "\n", ""
         )
 
-        m.submodules.now_cells = now_cells = Memory(shape=1, depth=GOL_CELLCNT, init=[c != "." for c in start])
+        m.submodules.now_cells = now_cells = \
+            Memory(shape=1, depth=GOL_CELLCNT, init=[c != "." for c in start])
         now_cells_rd = now_cells.read_port()
         now_cells_wr = now_cells.write_port()
         now_cells_addr = Signal.like(now_cells_rd.addr)
@@ -305,6 +290,11 @@ def cell_ix_at(x, y):
                     ili.cipo.eq(plat_spi.cipo.i),
                 ]
 
+                platform.add_resources([Resource("pmod_clk_out", 0,
+                    Subsignal("clk", Pins("1", dir="o", conn=("pmod", 0)), Attrs(IO_STANDARD="SB_LVCMOS")),
+                )])
+                m.d.comb += platform.request("pmod_clk_out").clk.o.eq(ClockSignal("sync"))
+
                 plat_uart = platform.request("uart")
                 m.d.comb += plat_uart.tx.o.eq(serial.tx.o)
                 m.submodules += FFSynchronizer(plat_uart.rx.i, serial.rx.i, init=1)

ili9341spi/targets.py

@@ -8,7 +8,8 @@
 
 
 class icebreaker(ICEBreakerPlatform):
-    if not os.getenv("GITHUB_ACTIONS"):
+    if False: # XXX: testing DDR SPI and this would make us run probably-too-fast for the LCD>
+    # if not os.getenv("GITHUB_ACTIONS"):
         # XXX: This meets timing when I build locally, but not on CI?!
         # https://github.com/kivikakk/ili9341spi/actions/runs/9535281535/job/26280812013?pr=1
         default_clk = "SB_HFOSC"