ad_quadmxfe1_ebz: Fix critical warnings

FilipG24 · FilipG24 · commit cf82a4a87db3 · 2025-02-25T16:28:15.000+02:00
-Connect adc/dac_sync_manual_req_in signals in the BD

Signed-off-by: Filip Gherman &lt;filip.gherman@analog.com&gt;
diff --git a/projects/ad_quadmxfe1_ebz/common/ad_quadmxfe1_ebz_bd.tcl b/projects/ad_quadmxfe1_ebz/common/ad_quadmxfe1_ebz_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2019-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -537,6 +537,13 @@ ad_connect  axi_mxfe_rx_jesd/rx_data_tvalid rx_mxfe_tpl_core/link_valid
 ad_connect ext_sync rx_mxfe_tpl_core/adc_tpl_core/adc_sync_in
 ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_rst util_mxfe_cpack/reset
 
+ad_ip_instance util_vector_logic manual_sync_or [list \
+      C_SIZE 1 \
+      C_OPERATION {or} \
+    ]
+ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_sync_manual_req_out manual_sync_or/Op1
+ad_connect manual_sync_or/Res rx_mxfe_tpl_core/adc_tpl_core/adc_sync_manual_req_in
+
 #
 # rx tpl to cpack
 #
@@ -640,6 +647,8 @@ for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
 }
 
 ad_connect ext_sync tx_mxfe_tpl_core/dac_tpl_core/dac_sync_in
+ad_connect tx_mxfe_tpl_core/dac_tpl_core/dac_sync_manual_req_out manual_sync_or/Op2
+ad_connect manual_sync_or/Res tx_mxfe_tpl_core/dac_tpl_core/dac_sync_manual_req_in
 
 #
 # dac fifo to upack
diff --git a/projects/ad_quadmxfe1_ebz/vcu118/system_project.tcl b/projects/ad_quadmxfe1_ebz/vcu118/system_project.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2019-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 

Original file line number	Diff line number	Diff line change
`@@ -1,5 +1,5 @@`
`1`	`1`	`###############################################################################`
`2`		`-## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.`
	`2`	`+## Copyright (C) 2019-2025 Analog Devices, Inc. All rights reserved.`
`3`	`3`	`### SPDX short identifier: ADIBSD`
`4`	`4`	`###############################################################################`
`5`	`5`
`@@ -537,6 +537,13 @@ ad_connect axi_mxfe_rx_jesd/rx_data_tvalid rx_mxfe_tpl_core/link_valid`
`537`	`537`	`ad_connect ext_sync rx_mxfe_tpl_core/adc_tpl_core/adc_sync_in`
`538`	`538`	`ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_rst util_mxfe_cpack/reset`
`539`	`539`
	`540`	`+ad_ip_instance util_vector_logic manual_sync_or [list \`
	`541`	`+ C_SIZE 1 \`
	`542`	`+ C_OPERATION {or} \`
	`543`	`+ ]`
	`544`	`+ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_sync_manual_req_out manual_sync_or/Op1`
	`545`	`+ad_connect manual_sync_or/Res rx_mxfe_tpl_core/adc_tpl_core/adc_sync_manual_req_in`
	`546`	`+`
`540`	`547`	`#`
`541`	`548`	`# rx tpl to cpack`
`542`	`549`	`#`
`@@ -640,6 +647,8 @@ for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {`
`640`	`647`	`}`
`641`	`648`
`642`	`649`	`ad_connect ext_sync tx_mxfe_tpl_core/dac_tpl_core/dac_sync_in`
	`650`	`+ad_connect tx_mxfe_tpl_core/dac_tpl_core/dac_sync_manual_req_out manual_sync_or/Op2`
	`651`	`+ad_connect manual_sync_or/Res tx_mxfe_tpl_core/dac_tpl_core/dac_sync_manual_req_in`
`643`	`652`
`644`	`653`	`#`
`645`	`654`	`# dac fifo to upack`